1. Field
This disclosure generally relates to the design of a translation lookaside buffer (TLB) in a computer system. More specifically, this disclosure relates to preventing duplicate entries in a non-blocking TLB that supports both multiple page sizes and speculative execution.
2. Related Art
Computer memory is typically divided into a set of fixed-length blocks called “pages.” An operating system can provide a virtual memory abstraction to give a program which is accessing such pages the impression that it is accessing a contiguous address space that is larger than the actual available physical memory of the underlying computer system. During operation, the operating system and hardware of the computing device translate virtual addresses accessed by the program into physical addresses in the physical memory.
Accessing a virtual address typically involves using specialized translation hardware to determine a corresponding physical memory address. This translation hardware often includes a translation lookaside buffer (TLB) which caches page table translation information to improve the speed of virtual address translations. In processor architectures that support two or more page sizes, this TLB may cache entries for multiple page sizes. However, problems can arise for processors that support multiple page sizes when the TLB does not know in advance the page size for a given translation request. In some instances, the TLB may become filled with multiple copies of the same translation information, which can cause costly multi-hit traps or pipe clears that lead to TLB invalidations and degrade processor performance.
Hence, what is needed are system structures and techniques for managing virtual address translation without the above-described problems of existing techniques.